Semiconductor Patent Drawing Examples for Devices and Processes

Semiconductor patent drawing examples typically show a device as layered semiconductor cross section views plus a top plan view, and a process as a fabrication process diagram with sequential steps. The goal is to teach structure and method clearly enough for an examiner to understand the invention without reading the specification first.

What makes semiconductor patent drawings different

Semiconductor figures are denser than mechanical drawings. A single chip patent figure may contain a substrate, wells, gates, contacts, interconnects, and dielectric layers, each needing a distinct reference numeral and consistent hatching. Small geometry errors can change claim scope, so precision matters more than visual appeal.

Patent offices generally expect black-and-white line art, no photographs, and no color unless a petition is granted. Shading is allowed only for specific purposes, such as indicating a spherical surface or contrasting a cross section. For semiconductor work, cross-hatching is the standard way to differentiate materials.

Common semiconductor patent drawing examples by type

Device structure figures

Device figures show the final structure of a transistor, diode, memory cell, sensor, or package. The most useful format is a semiconductor cross section taken along a cut line marked on an accompanying top view. A typical CMOS example includes a silicon substrate, source and drain regions, a gate stack, spacers, contacts, and metal interconnect layers, each labeled with a numeral that matches the specification.

Fabrication process diagrams

A fabrication process diagram illustrates a method claim as a sequence of cross sections, usually labeled FIGS. 2A through 2F. Each figure shows one meaningful change: depositing a layer, patterning a mask, etching, implanting, or planarizing. The convention is to keep the same reference numeral for the same feature across all steps and add new numerals only when a new feature appears.

Circuit and block diagrams

Many semiconductor patents combine physical structure with electrical function. A block diagram may show a memory array, row decoder, sense amplifier, and controller, while a schematic shows transistor-level connections. These follow standard electronic symbol conventions and must remain readable at the required reproduction size.

Layout and mask figures

For inventions involving photomasks or integrated circuit layout, top plan views show geometric patterns of diffusion regions, polysilicon lines, and contacts. These are often drawn to scale and may include a legend explaining line styles or fill patterns.

How to draft a semiconductor cross section step by step

Follow this workflow to produce a defensible semiconductor cross section drawing:

1. List every feature claimed. Read the independent claims first. Every structural limitation needs a visible, labeled element in at least one figure.
2. Choose the cut line. Place the cross-section indicator on the top plan view so it passes through the most important structures.
3. Draw the substrate first. Start with the deepest layer and build upward in deposition order. This matches how the specification describes the structure.
4. Assign reference numerals in order of first mention. The first element described in the specification should be numeral 10 or 100, the next 20 or 110, and so on. Never reuse a numeral for a different feature.
5. Apply hatching consistently. Use one hatch pattern per material class across all figures. Keep the same pattern for silicon dioxide, metal, and photoresist throughout the entire application.
6. Add leader lines that touch the element. Each leader line should end with a dot or arrowhead on the feature and point outward to the numeral. Avoid crossing leader lines where possible.
7. Check scale and line weight. Lines must remain distinct when the figure is reduced to two-thirds size for publication. A 0.2 mm minimum line thickness is a common working rule.

Worked example: a fin field-effect transistor

Suppose the invention is a finFET with a strained channel. The drawing set would include:

• FIG. 1: a top plan view showing the fin, gate, source, and drain regions, with a cut line A-A′ marked.
• FIG. 2: a semiconductor cross section along A-A′ showing the fin rising from the substrate, the gate dielectric wrapping the fin, and the gate electrode over the gate dielectric.
• FIG. 3: a cross section perpendicular to the fin showing the strained channel material between source and drain.
• FIGS. 4A-4D: a fabrication process diagram showing fin formation, dummy gate deposition, source/drain recess, and strained material epitaxial growth.

In this set, the substrate might be numeral 100, the fin 110, the gate dielectric 120, the gate electrode 130, the source region 140, and the drain region 150. The same numerals appear in every figure, which is exactly what makes the drawing set teach the invention coherently.

Common mistakes in semiconductor patent drawings

• Mismatched numerals. A feature labeled 210 in the drawing but described as 220 in the text creates confusion and can support a rejection for indefiniteness.
• Inconsistent hatching. Using a different hatch pattern for the same material in different figures makes it hard to compare process steps.
• Missing cut line. A cross section without a corresponding top view and cut line leaves the examiner guessing where the section is taken.
• Overcrowded labels. Too many numerals in one figure reduce legibility. Split complex structures into multiple figures or partial enlarged views.
• Color reliance. Submitting color figures without a petition, or using color as the only differentiator, creates rejection risk and poor black-and-white reproduction.
• No process continuity. In a fabrication process diagram, a layer that disappears between steps without explanation suggests an unclaimed or unclear step.

How PatentDraw helps

PatentDraw provides an AI-assisted workspace for generating and refining chip patent figures, including semiconductor cross sections and process sequences. You can start from a text description of the structure, generate a draft figure, then adjust layers, labels, and hatching before export. Because AI output is a working draft, every figure still requires human technical and professional review against the claims and specification before filing.

Frequently asked questions

What is a semiconductor cross section in a patent drawing?

A semiconductor cross section is a cut-away view showing the internal layered structure of a device, such as a transistor or memory cell. It reveals the vertical arrangement of substrate, doped regions, dielectric layers, and interconnects that a top view cannot show. Cross sections are the primary way structural claims are illustrated.

How many figures does a semiconductor patent need?

There is no fixed number, but most semiconductor applications include at least one top plan view, one or more cross sections, and a sequence of process figures. Complex inventions may use ten to twenty figures plus enlarged partial views. The key requirement is that every claimed feature appears in at least one figure.

Can semiconductor patent drawings use color or photographs?

Normally no. Utility patent drawings must be black-and-white line art unless color is necessary and a petition under 37 CFR 1.84(a)(2) is granted. Photographs are allowed only where they are the only practical medium, which is rare for semiconductor structures. Hatching and line styles are the accepted alternatives.